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| RFP4N100, RF1S4N100SM Data Sheet August 1999 File Number 2457.4 4.3A, 1000V, 3.500 Ohm, High Voltage, N-Channel Power MOSFETs The RFP4N100 and RFP4N100SM are N-Channel enhancement mode silicon gate power field effect transistors. They are designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from an integrated circuit. Formerly developmental type TA09850. Features * 4.3A, 1000V * rDS(ON) = 3.500 * UIS Rating Curve (Single Pulse) * -55oC to 150oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol D Ordering Information PART NUMBER RFP4N100 RF1S4N100SM PACKAGE TO-220AB TO-263AB BRAND RFP4N100 F1S4N100 G S NOTE: When ordering, use the entire part number. Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE JEDEC TO-263AB DRAIN (FLANGE) 4-528 CAUTION: These devices are sensitive to electrostatic discharge; follow properS ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 RFP4N100, RF1S4N100SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFP4N100, RF1S4N100SM Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 1000 1000 4.3 17 20 (See UIS SOA Curve) (Figures 4, 14, 15) 150 1.2 -55 to 150 300 260 UNITS V V A A V mJ W W/oC oC oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 10) VGS = VDS, ID = 250A VDS = 1000V, VGS = 0V VDS = 800V, VGS = 0V, TC = 150oC MIN 1000 2 VGS = 20V, ID = 3.9A, VDS = 800V (Figure 13) TYP MAX 4 25 100 100 3.500 30 50 170 50 120 UNITS V V A A nA ns ns ns ns nC oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient IGSS rDS(ON) td(ON) tr td(OFF) tf Qg(TOT) RJC RJA VGS = 20V ID = 2.5A, VGS = 10V (Figures 8, 9) VDD = 500V, ID 3.9A, RGS = 9.1, RL = 120) - - 0.83 62 Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time NOTES: 2. Pulse test: pulse width 80s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. SYMBOL VSD trr ISD = 4.3A ISD = 3.9A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.8 1000 UNITS V ns 4-529 RFP4N100, RF1S4N100SM Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 TC = 25oC, Unless Otherwise Specified 4.5 4.0 0.6 0.4 0.2 0.0 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 100 RFP4N100, RF1S4N100SM ID, DRAIN CURRENT (A) 10s 100 IAS, AVALANCHECURRENT (A) IF R = 0 tav = (L)(Ias) / (1.3 x RATED BVDSS - VDD) IF R 0 tav = (L/R) In ((Ias x R) / (1.3 x RATED BVDSS - VDD) + 1) 10 100s 1ms Idm 10 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED SINGLE PULSE STARTING TJ = 25oC STARTING TJ = 150oC 10ms 0.1 DC 0.01 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 1000 1 0.01 0.10 1 tAV, TIME IN AVALANCHE (ms) 10 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA 10 VGS = 10V 10 VGS = 6V ID, DRAIN CURRENT (A) 8 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V VGS = 6V ID, DRAIN CURRENT (A) 8 6 VGS = 5V 4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 6 VGS = 5V 4 2 VGS = 4V 0 0 100 200 300 400 VDS, DRAIN TO SOURCE VOLTAGE (V) 500 2 VGS = 4V 0 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) 50 FIGURE 5. OUTPUT CHARACTERISTICS FIGURE 6. SATURATION CHARACTERISTICS 4-530 RFP4N100, RF1S4N100SM Typical Performance Curves IDS(ON), DRAIN TO SOURCE CURRENT (A) 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS = 15V TC = 25oC, Unless Otherwise Specified (Continued) 6 VGS = 10V PULSE DURATION = 80s 5 DUTY CYCLE = 0.5% MAX ON RESISTANCE () 4 3 2 1 0 4 3 2 150oC 1 25oC 0 rDS(ON), DRAIN TO SOURCE 0 2 4 6 VGS, GATE TO SOURCE VOLTAGE (V) 8 0 2 4 6 8 ID, DRAIN CURRENT (A) 10 12 FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENT 3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = 10V, ID = 4.3A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.3 ID = 250A 1.2 2.5 2.0 1.1 1.5 1.0 1.0 0.9 0.5 -50 0.8 0 50 100 TJ , JUNCTION TEMPERATURE (oC) 150 -40 80 0 40 120 TJ , JUNCTION TEMPERATURE (oC) 160 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 3000 2500 C, CAPACITANCE (pF) 2000 1500 1000 CRSS 500 0 CISS ID, SOURCE TO DRAIN CURRENT (A) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 100 TJ = 150oC 10 TJ = 25oC COSS 1 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 0 0.3 0.6 0.9 1.2 VSD, SOURCE TO DRAIN VOLTAGE (V) 1.5 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 12. DRAIN CURRENT vs SOURCE TO DRAIN DIODE VOLTAGE 4-531 RFP4N100, RF1S4N100SM Typical Performance Curves 16 VGS, GATE TO SOURCE VOLTAGE (V) ID = 3.9A VDS = 100V VDS = 200V VDS = 400V 8 TC = 25oC, Unless Otherwise Specified (Continued) 12 4 0 0 20 40 60 Qg, TOTAL GATE CHARGE (nC) 80 FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS 4-532 RFP4N100, RF1S4N100SM Test Circuits and Waveforms (Continued) VDS RL VDD VDS VGS = 20V VGS + Qg(TOT) Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V DUT Ig(REF) FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-533 |
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